1. Field of the Invention
This invention relates to combined bipolar and CMOS (BiCMOS) semiconductor integrated circuits (ICs). More particularly, the invention relates to a circuit for converting emitter coupled logic (ECL) levels to complementary metal oxide semiconductor (CMOS) logic levels for BiCMOS applications.
2. Description of the Related Art
BiCMOS technology combines the speed advantage of bipolar circuitry with the low power consumption advantage of CMOS circuitry. Conventional ECL and CMOS circuits on a BiCMOS IC may have the same operating voltage range, but they may have differing voltage rages with respect to their high and low logic levels. Accordingly, the presence of both ECL and CMOS circuitry on the BiCMOS IC necessitates the use of internal ECL to CMOS converters.
For example, a typical ECL circuit operates within five volt differential range (+5 to 0.0 volts), with 5 and 4.5, 4.2 and 3.7, 3.4 and 2.9, 2.8 and 2.3 representing pairs of typical logic low and logic high voltage levels, respectively. The selected voltage values depend on supply voltage, temperature, and process conditions. In contrast, a typical CMOS circuit operates within a 3.3 volt differential range, with 3.3 and 0 volts representing logic high and low levels, respectively.
U.S. Pat. No. 5,068,551 discloses an ECL to CMOS converter wherein an ECL logic circuit is coupled through a pair of emitter followers to the corresponding input nodes of a translation circuit. The translation circuit includes two pairs of crossed-coupled N-channel transistors. The complementary output nodes of the translation circuit are coupled to a corresponding pair of PMOS transistors. A refresh circuit which includes two CMOS inverters having cross-coupled input and output nodes, is also coupled to the complementary output nodes of the converter.
The operation of the '551 logic converter is as follows. The two emitter followers supply a pair of complementary ECL output signals to the complementary input nodes of the translation circuit. In response, the translation circuit turns the appropriate PMOS transistor on, thereby presenting a high CMOS logic level at the corresponding output node of the converter.
The high output signal at the one of the output nodes of the logic converter drives the corresponding input node of the refresh circuit high, causing the refresh circuit to latch, and regeneratively driving and maintaining both complementary output voltages at the output nodes of the converter.
The ECL to CMOS translator disclosed by the '551 patent has a number of deficiencies. Only one of two PMOS transistors coupled between the translation circuit and the output nodes of the converter is turned on during switching, i.e., the corresponding PMOS transistor is off. A full voltage swing of both PMOS transistors is required before the ECL to CMOS converter can switch to the opposite state. As such, the switching time of the converter circuitry is relatively slow. This problem is compounded by the refresh circuitry which imposes an additional load on the output nodes and further slows down the switching speed of the prior art converter.